1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a W-CSP semiconductor device having a Through Silicon VIA (TSV) electrode structure.
2. Description of the Related Art
In recent years, a remarkable progress in terms of miniaturization and increase in density and functionality has been achieved in the field of information devices such as digital cameras and cellular phones equipped with cameras. A wafer-level chip size package (hereinafter referred to as W-CSP) that realizes a package of a chip size is known as a technique for miniaturizing image sensors such as CCD sensors and CMOS sensors installed at the aforementioned devices. The W-CSP is a new concept package in which the entire assembly process is completed in a wafer state.
A Through Silicon VIA electrode (hereinafter, referred to as “TSV electrode”) structure has been used in an image sensors of a W-CSP structure because reliability can be improved and the device can be miniaturized. An electrode for exchanging signals between a semiconductor device and an external device is usually formed on the same plane as a semiconductor elements formation plane. By contrast, in case of a TSV electrode, a Through Silicon VIA hole (hereinafter, referred to as “TSV hole”) is formed in the thickness direction of the chip by etching from the reverse side of the chip using a fine processing technology, a conductive wiring is formed inside the TSV hole so as to connect to a top surface electrode pad, thereby making it possible to exchange signals from the reverse surface of the chip that is usually not used. By stacking a plurality of chips using a TSV electrode technique and forming a signal transmission path in the thickness direction of the chips, it is possible to shorten the wiring length in comparison with that of the conventional wiring. Therefore, packaging density can be dramatically improved and operating speed and reliability of the device can be increased.
Japanese Patent Applications Laid-open Nos. 2005-235858 and 2008-140819 disclose CSP structures having a TSV electrode, and Japanese Patent Application Laid-open No. 2002-83949 discloses a CMOS image sensor structure.
For example, a CMOS sensor is a type of image sensor that converts an electric charge accumulated in a photodiode into a voltage at respective pixels, amplifies the voltage, and then reads the voltage. A CMOS sensor is provided with a photodiode and a cell amplifier in a unit cell. A CMOS sensor is constituted by a plurality of active elements that constitute a photodiode and a cell amplifier, and an STI (Shallow Trench Isolation) is formed for insulating and separating the active elements from each other. Here, a region for forming active elements such as transistors and diodes on a semiconductor substrate is called an active area. A region other than the active area is called a non-active area. In other words, an element separation region such as STI belongs to the non-active area. In the process of forming an STI on a semiconductor substrate, planarization by CMP (Chemical Mechanical Polishing) is performed. When a surface area of an STI region increases, a dishing occurs due to a difference in polishing rates between an oxide film constituting the STI and a nitride film provided as a stopper during polishing. Namely, a dish-like concavity appears in a central portion of the STI. When a dishing occurs, planarity of the substrate is degraded and subsequent processing is therefore made difficult. A dummy pattern having a plurality of island-shaped dummy portions is formed in the non-active area that is the dishing occurrence region to prevent the dishing. The dummy pattern is formed by leaving a base material of a semiconductor substrate in island shapes inside the STI region, and is therefore referred to as a “dummy active portion”. Dishing can be prevented because a difference in polishing rates in a CMP process is lessened by the uniform formation of dummy active portions in the non-active area (STI region).
By the way, a salicide technology is known as a technique for decreasing a resistance of a gate wiring and a source-drain diffusion layer of a transistor. In a salicide process, compound layers of a high-melting metal (silicide layers) are formed at the same time in both a source-drain diffusion layer and a gate polysilicon layer, thereby reducing a delay caused by a resistance component and realizing a high-speed operation. Because a metal material for forming a silicide layer is usually formed over the entire surface of a wafer to improve productivity, the silicide layer is formed not only in the active area having active elements, but also on the dummy active portions in the non-active area where no active elements are formed.
In an image sensor of a W-CSP structure, a sensor area having a sensor element group formed therein is disposed in the center of the sensor chip, whereas the non-active area is disposed on the outside of the sensor area. Further, in a usual configuration, the TSV electrodes are formed in the non-active area outside the sensor area, and dummy active portions are formed in the non-active area in order to prevent the above-described dishing. Thus, in a process of manufacturing an image sensor of a W-CSP type that uses a salicide technology, the TSV holes that passes through the silicide layer formed on the dummy active portions are formed by a dry etching method. The inventors have discovered that when the TSV hole intersects with the silicide layer in a dry etching process, notches (outwardly expanding depressions in the side wall of the TSV hole) appear in the side wall of the TSV hole. How such notches appear will be explained below in greater detail.
FIG. 1 is a plan view illustrating a surface structure of a semiconductor substrate in the vicinity of a TSV electrode formation portion. A broken line in the figure shows an outer edge of the TSV electrode (TSV hole) that intersects with this plane. A TSV hole 21 that has an almost cylindrical shape is formed within a non-active area 100 in which no active element such as a CMOS sensor is formed. An STI layer 110 composed of a SiO2 film is extended in the non-active area 100, and a plurality of island-shaped dummy active portions 200a are uniformly disposed on the SiO2 film for dishing prevention. In a semiconductor device using the salicide technology, a silicide layer is also formed on the dummy active portions 200a when the silicide layer is formed on the active elements in the active area (not shown in the figure). The TSV hole 21 is formed so as to pass through the non-active area 100 having arranged therein a plurality of dummy active portions 200a having the silicide layer on the surface. When the size and arrangement spacing of the dummy active portions 200a are less than the size of the TSV hole 21, the outer edge of the TSV hole 21 intersects with the dummy active portions 200a. 
FIG. 2 is a cross-sectional view along the 2-2 line in FIG. 1. An interlayer insulating film 12 is formed on a semiconductor substrate 10, and an electrode pad 13 electrically connected to a sensor portion is formed in the interlayer insulating film 12. The TSV hole 21 is formed by dry etching from the reverse surface of the semiconductor substrate toward the electrode pad 13. It was found out that when in the dry etching process, the outer edge of the TSV hole 21 intersects with the dummy active portions 200a having silicide layer 210, notches 300, which are a depressed portion of the side wall of the TSV hole 21, appear at the depth position of near the interface between the semiconductor substrate 10 and the interlayer insulating film 12. In FIG. 1, the locations where notches 300 are appeared are shown by hatching. As shown in FIG. 1, it can be found that the notches 300 appear only in the locations where the outer edge of the TSV hole 21 intersects with the dummy actives 200a. 
In the process of forming a TSV electrode, the TSV hole 21 is formed and then, a barrier metal, a plating seed film, and a plating film are successively formed on the inner wall of the TSV hole. Cu is generally used as the plating film, but Cu is a typical material of metal contamination for silicon devices. Cu can diffuse to the semiconductor substrate or interlayer insulating film at a comparatively low temperature and degrade the device performance and reliability, for example, by causing a junction leak or insulation breakdown of the interlayer insulating film. Therefore, a barrier metal such as Ti or Ti/Ni is provided between the semiconductor substrate and the Cu film constituting a conductive wiring of the TSV electrode in order to prevent the Cu-diffusion into the semiconductor substrate.
However, when notches appear at the side wall of the TSV hole, it is difficult to form a sufficient barrier metal at the notch appearance portions and there is a risk of causing a lacking portion of the barrier metal in the notch appearance portions. In this case, Cu could diffuse into the semiconductor substrate in the areas where there is insufficient coverage by the barrier metal, and the device performance and reliability are seriously affected.